Asynchronous Transfer Mode ("ATM") switches are used in a switching network to route ATM cells. In particular, an ATM switch receives an ATM cell at one of its input ports and routes the cell to one of its output ports based on routing information contained within the cell. Each ATM cell is a fixed length data packet having a header section and a data section. FIG. 5 shows an example of a conventional ATM switch that includes output buffers for storing ATM cells. Typically, such ATM switches are realized as one or more integrated circuit chips.
The ATM switch of FIG. 5 is an 8.times.8 switch. That is, the switch includes eight input ports IP#0-IP#7 for inputting ATM cells, and eight output ports OP#0-OP#7 for outputting ATM cells. In this example, each of the input and output ports transfers ATM cells at a rate of 155 Mbps. Additionally, the ATM cells each have a data length of 64 bytes, including a header portion and a data portion. The header portion includes an output port tag to identify the output port to which the ATM cell is to be routed by the switch.
The ATM cells input to one of the input ports IP are first stored in a FIFO (first in, first out buffer) 10-17 that is provided for the input port. Output port tag information included in an ATM cell stored in the FIFO is read out at the beginning of each cell cycle by a header analysis portion 21 of a control portion 20. The header analysis portion 21 controls the switching operation of a cross bar switch (CRBSW) 22 on the basis of the tag information. More specifically, an output buffer 30-37 is provided for each of the output ports OP#0 to OP#7. The ATM cell is transferred from the FIFO to the output buffer 30-37 corresponding to the output port indicated by the cell's tag information. Generally, each output buffer 30-37 can store multiple ATM cells. A cell counter 40-47 is provided for each of the output buffers 30-37 to keep a count of the number of ATM cells stored in the corresponding output buffer. The cell counters 40-47 receive control signals (namely, increment signals INC0-INC7 and decrement signals DEC0-DEC7) from the control portion 20 that are used by the cell counters to carry out the counting operation.
In the ATM switch of FIG. 5, an output buffer may become filled so that further ATM cells destined for the corresponding output port must be abandoned. For example, consider the case where each of the output buffers 30-37 can store up to six ATM cells. If eight ATM cells are input into the input ports IP in one cell cycle and all eight ATM cells are destined for the same output port OP, then the capacity of the selected output port OP is exceeded. Therefore, there is an overflow and ATM cells must be abandoned. An abandoned cell counter 23 receives a control signal INCD from the control portion 20 in order to count the number of ATM cells (DCCQ, discard cell counter output) that are abandoned by the ATM switch.
ATM switches used in public networks and the like operate continuously for a long period of time (for example, several tens of years). However, the conventional ATM switch does not verify that its cell counters are operating properly. This presents a problem because once a cell counter begins malfunctioning, the number of ATM cells stored in the corresponding output buffer does not match the number reported by the cell counter. If the ATM switch continues to be operated under such conditions, it may malfunction or perform the switching operation poorly. Thus, a conventional ATM switch cannot provide the degree of reliability required for commercial applications.
Additionally, a host processor (not shown) supervises the operation of the ATM switch. The host processor monitors information received from the ATM switch, such as the number of ATM cells stored in each output buffer and the number of cells that have been abandoned. Using this information, the host processor can insure the best flow of ATM cells through a switching system having many ATM switches. However, once one of the cell counters in the conventional ATM switch begins to malfunction, the host processor receives an inaccurate cell count so the flow control performed by the host processor is disturbed. Accordingly, the performance of the entire switching system is reduced.